Home : Faculty :

Kewal K. Saluja

2010-

	Lists of Publications
	1969
	1970-1979
	1980-1989
	1990-1999
	2000-2009

List of Publications

• List of Books (5) (in LATEX .bib format)
• List of Publication (Journal papers) (in LATEX .bib file format)
• List of Publication (Primary Conference papers) (in LATEX .bib file format)
• List of Publication (Secondary Conference papers+) (in LATEX .bib file format)

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1969

1. S. N. Roy, V. N. Rikh, and K. K. Saluja, " Salient features of the 400 kv line for U.P.," Indian Journal of Power and River Valley Development, pp. 407-412, 422, October 1969.

1970-1979

2. K. K. Saluja and S. M. Reddy, "Multiple faults in Reed-Muller canonic networks," Proc. 13th Annual Symp. on Switching and Automata Theory, pp. 185-191, October 1972.
3. K. K. Saluja and S. M. Reddy, "On minimally testable logic networks," IEEE Trans. on Computers, vol. C-23, pp. 552-554, May 1974.
4. K. K. Saluja and S. M. Reddy, "Easily testable two-dimensional cellular logic arrays," IEEE Trans. on Computers, vol. C-23, pp. 1204-1207, November 1974.
5. K. K. Saluja and F. J. Lidgey, A novel approach to fault diagnosis in Gunn effect logic circuits, Proc. IREE International Electronics Convention, pp. 13-16, August 1975.
6. K. K. Saluja and S. M. Reddy, "Fault detection test sets for Reed-Muller canonic networks," IEEE Trans. on Computers, vol. C-24, pp. 995-998, Oct 1975.
7. K. K. Saluja and F. J. Lidgey, "Fault diagnosis in Gunn logic networks," Digest International Symposium on Fault Tolerant Computing, pp. 202, June 1976.
8. K. K. Saluja, "A testable design of sequential machines," Digest International Symposium on Fault Tolerant Computing, pp. 185-190, June 1978.
9. K. K. Saluja, "A note on transition equation method for realization of sequential machines," Proc. IREE Australia, pp. 119-120, August 1978.
10. K. K. Saluja and E. H. "Ong, Minimization of Reed-Muller canonic expansion," IEEE Trans. on Computers, vol. C-28, pp. 535-537, July 1979.
11. K. K. Saluja and F. J. Lidgey, "Fault detection in Gunn logic: Some preliminary experimental results," Digest IREE International Electronics Convention, pp. 414-417, August 1979.
12. K. K. Saluja, "System level diagnosis: A survey," Digest IREE International Electronics Convention, pp. 128-131, August 1979.
13. K. K. Saluja and B. D. O. Anderson, "t-fault (t/2)-step sequentially diagnosable systems," Proc. IEEE, vol. 697, pp. 1678-1979, December 1979.

1980-1989

14. C. S. Venkatraman and K. K. Saluja, "Trends in fault-tolerant computing," Digest of Conference on Digital System Design, pp. 18-23, May 1980.
15. K. K. Saluja and S. J. Wiche, "A self-testing microprocessor-based system," Digest of Conference on Digital System Design, pp. 52-56, May 1980.
16. K. K. Saluja and B. D. O. Anderson, "Fault diagnosis in loop-connected systems," Information Sciences, vol. 21, pp. 75-92, June 1980.
17. G. C. Goodwin, K. S. Sin, and K. K. Saluja, "Stochastic adaptive control and prediction : The general delay-coloured noise case," IEEE Trans. on Auto. Control, vol. AC-25, pp. 946-950, October 1980.
18. C. S. Venkatraman and K. K. Saluja, "Transition count testing of sequential machines," Digest International Symposium on Fault Tolerant Computing, pp. 167-172, October 1980.
19. K. K. Saluja, "Synchronous sequential machines - a modular and testable design," IEEE Trans. on Computers, vol. C-29, pp. 1020-1025, November 1980.
20. K. K. Saluja and F. J. Lidgey, "Fault detection in combinational circuits using Gunn effect logic devices," Electronics Letters, vol. 17, pp. 222-223, March 1981.
21. K. K. Saluja, K. Kinoshita, and H. Fujiwara, "A multiple-fault testable design of programmable logic arrays," Digest International Symposium on Fault Tolerant Computing, pp. 44-46, June 1981.
22. K. K. Saluja and B. D. O. Anderson, "Easily diagnosable design at system level," Digest of Conf. on Computers in Engineering Melbourne, pp. 59-65, September 1981.
23. K. K. Saluja and S. M. Reddy, "A class of undirected graphs," Digest of 1981 Conference on Information Sciences and Systems, 1981.
24. K. K. Saluja, "A diagnosable design of programmable logic arrays," Proc. Microelectronics - 82, pp. 94-101, May 1982.
25. K. K. Saluja, "An enhancement of LSSD to reduce test pattern generation and increase fault coverage," Proc. 19th Design Automation Conference, pp. 489-494, June 1982.
26. C. R. Kime and K. K. Saluja, "Test scheduling in testable VLSI circuits," Digest International Symposium on Fault Tolerant Computers, pp. 406-412, June 1982.
27. S. Chandra and K. K. Saluja, "Fault location in sequential trees," Proc. Twentieth Allerton Conference on Communication Control and Computing, pp. 209-218, October 1982.
28. K. K. Saluja and C. S. Venkatraman, "Generalized data compression for VLSI testing," Proc. Twentieth Allerton Conference on Communication Control and Computing, pp. 229-230, October 1982.
29. K. K. Saluja, "A survey of testable designs in VLSI," Proc. Aust. Computer Engineering Symposium-1, pp. 5.1-5.7, Aug 1983.
30. I. Lawrence, K. K. Saluja, and B. Hunter, "Microprocessor-based remote metering system," Proc. Conference on Computers and Engineering, pp. 49-52, August 1983.
31. K. K. Saluja and S. Su, "VLSI testing through data compression: A survey," Digest IREE International Electronics Convention, pp. 142-144, September 1983.
32. K. K. Saluja and R. Dandapani, Comments on a data compression technique for VLSI testing, Proc. 21st Allerton Conference on Communication Control and Computing, October 1983. J. S. Upadhyaya and K. K. Saluja, Is fault location possible using linear feedback shift registers, Workshop on Spectral Methods, October 1983.
33. K. K. Saluja, L. Shen, and S. Y. H. Su, "A simplifier algorithm for testing microprocessors," Proc. Int. Test Conference, pp. 18-20, October 1983.
34. K. K. Saluja and M. Karpovsky, "Testing computer hardware through data compression in space and time," Proc. Int. Test Conference, pp. 18-20, October 1983.
35. K. K. Saluja, K. Kinoshita, and H. Fujiwara, "An easily testable design of programmable logic arrays for multiple faults," IEEE Trans. on Computers, vol. C-32, pp. 1038-1046, November 1983.
36. J. S. Upadhyaya and K. K. Saluja, "A hardware-supported general rollback technique," Digest International Symposium on Fault Tolerant Computing, pp. 409-414, June 1984.
37. K. Kinoshita and K. K. Saluja, "Built-in testing of memory using on-chip compact testing scheme," Proceedings of IEEE International Test Conference, pp. 271-281, October 1984.
38. K. K. Saluja and R. Dandapani, "Testable design of sequential machines using compaction function and checking experiment," Proceedings 22nd Allerton Conference on Communication, Control and Computing, pp. 121-127, October 1984.
39. K. K. Saluja and K. T. Le, "Testable design of large random access memories," Integration - The VLSI Journal, vol. 2, pp. 309-330, December 1984.
40. K. K. Saluja and K. Kinoshita, "Test pattern generation for API faults in RAMs," IEEE Transactions on Computers, vol. C-34, pp. 284-287, March 1985.
41. K. K. Saluja and J. S. Upadhyaya, "Divide and conquer strategy for testable design of programmable logic arrays," 4th Australian Microelectronics Conference, pp. 121-127, May 1985.
42. K. K. Saluja and R. Dandapani, "Generalized compaction function testable design of sequential machines using checking experiments, " Digest International Symposium on Fault Tolerant Computing, pp. 306-311, June 1985.
43. S. M. Reddy, K. K. Saluja, and M. Karpovsky, "A data compression technique for built-in self test," Digest International Symposium on Fault Tolerant Computing, pp. 294-299, June 1985.
44. K. K. Saluja, K. Kinoshita, and C. Boswell, "A design of parallel testable programmable logic arrays," International Symposium on Circuits and Systems, pp. 1325-1328, June 1985.
45. J. S. Upadhyaya and K. K. Saluja, "Signature techniques in fault detection and location," in Fault Detection and Spectral Techniques, M. Karpovsky, editor, pp. 421-475, Ed., Academic Press, August 1985.
46. C. Boswell, K. K. Saluja, and K. Kinoshita, "A design of programmable logic arrays for parallel testing," Journal of Computer System Science and Engineering, vol. 1, pp. 5-16, October 1985.
47. P. Sheen, R. Dandapani, and K. K. Saluja, "A test pattern generator with embedded compressed outputs for built-in self-test," Proceedings 23rd Annual Allerton Conference on Communication Control and Computing, October 1985.
48. K. K. Saluja, H. Fujiwara, and K. Kinoshita, "A testable design of programmable logic arrays with universal control and minimal overhead," Proceedings of the IEEE International Test Conference, pp. 574-582, November 1985.
49. J. S. Upadhyaya and K. K. Saluja, "A watchdog processor-based general rollback technique with multiple retries," IEEE Transactions on Software Engineering (Special Issue on Software Reliability), vol. SE-12, pp. 87-95, January 1986.
50. K. T. Le and K. K. Saluja, "A built-in self-testing design for large random access memories," Built-In Self-Test Workshop (Poster Session), March 1986.
51. K. K. Saluja and R. Dandapani, "An alternative to scan design methods for sequential machines," IEEE Transactions on Computers (Special Issue on Fault Tolerant Computing), vol. C-35, pp. 384-388, April 1986.
52. R. Dandapani and K. K. Saluja, "Checking experiment testable design of small sequential machines," Design for Testability Workshop, May 1986.
53. S. Y. H. Su, K. K. Saluja, and M. Wang, "Fault-tolerant VLSI systolic architecture," Digest International Conference on Fault Tolerant Systems and Diagnosis, pp. 36-44, June 1986.
54. K. K. Saluja and R. Dandapani, "Testable design of single-output sequential machines using checking experiments," IEEE Transactions on Computers, vol. C-35, pp. 658-662, July 1986.
55. K. K. Saluja and R. Dandapani, "A built-in self-testable design method for sequential circuits," Digest International Symposium on Fault Tolerant Computing, pp. 312-317, July 1986.
56. S. Y. H. Su, M. Cutler, M. Wang, and K. K. Saluja, "Fault-tolerant VLSI/LSI systolic architecture via built-in self-test," Proc. International Workshop on Systolic Arrays, pp. N1.1-N1.12, July 1986.
57. K. T. Le and K. K. Saluja, "A novel approach for testing memories using a built-in self-testing technique," Proceedings of the International Test Conference, pp. 830-839, September 1986.
58. K. Kinoshita and K. K. Saluja, "Built-in testing of memory using on-chip compact testing scheme," IEEE Transactions on Computers, vol. C-35, pp. 862-870, October 1986.
59. K. K. Saluja and J. S. Upadhyaya, "A built-in self-testing programmable logic array with high fault coverage," Proceedings of the IEEE International Conference on Computer Design, pp. 596-599, October 1986.
60. J. T. King, R. Dandapani, and K. K. Saluja, "An experimental study of test pattern and response compression technique for BIST," Proceedings 24th Annual Allerton Conference on Communication, Control and Computing, pp. 916-924, October 1986.
61. S. Su, M. Cutler, M. Wang, and K. Saluja, "Self-diagnosis of linear and mesh systolic arrays by signature comparison, in Systolic Arrays, " A. M. W. Moore and R. Urquhart, editors, pp. 217-227, Ed., Adam Hilger, Bristol and Boston, 1987.
62. K. K. Saluja, S. H. Song, and K. Kinoshita, "Built-in self-testing RAM: A practical alternative," IEEE Design and Test of Computers (also appeared in the Selected Reprints from Computer Society Magazines published by the IEEE Computer Society), vol. 4, pp. 42-51, February 1987.
63. K. K. Saluja, H. Fujiwara, and K. Kinoshita, "A testable design of programmable logic arrays with universal control and minimal overhead," International Journal of Computers and Mathematics with Applications, vol. 13, pp. 503-517, February 1987.
64. K. K. Saluja, L. Shen, and S. Y. H. Su, "A simplified algorithm for testing microprocessors," International Journal of Computers and Mathematics with Applications, vol. 13, pp. 431-441, February 1987. (Invited paper)
65. K. K. Saluja, R. Sharma, and C. R. Kime, An on-line BIST technique using off-line BIST resources, Built-In Self-Test Workshop, March 1987.
66. C. Y. Liu, K. K. Saluja, and J. S. Upadhyaya, "BIST-PLA: A built-in self-test design of large programmable logic arrays," Proc. 24th Design Automation Conference, pp. 385-391, June 1987.
67. K. Cheung, G. Sohi, K. Saluja, and D. Pradhan, "Organization and analysis of a gracefully-degrading interleaved memory," Proc. IEEE/ACM 14th Int. Symposium on Computer Architecture, June 1987.
68. C. R. Kime, K. K. Saluja, R. Sharma, and L. Sigal, "Concurrent testing methods for digital logic," Midwest Testability Workshop, National Security Industries Association, July 1987.
69. K. Akiyama and K. K. Saluja, "Transition count as a compression function in built-in self-test environment," Proceedings 25th Annual Allerton Conference on Communication, Control and Computing, pp. 1069-1078, October 1987.
70. K. K. Saluja, R. Sharma, and C. R. Kime, "Concurrent comparative testing using BIST resources," Proc. IEEE International Conference on Computer Aided Design, pp. 336-339, November 1987.
71. K. K. Saluja and S. M. Reddy, "On detection of bridging faults in programmable logic arrays," International Symposium on Electronic Devices, Circuits and Systems, pp. 699-701, December 1987.
72. J. S. Upadhyaya and K. K. Saluja, "A new approach to the design of built-in self-testing PLAs for high fault coverage," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Special issue on Testing), vol. 7, pp. 60-67, January 1988.
73. R. Sharma and K. K. Saluja, "An implementation and analysis of a concurrent built-in self-test technique," Digest International Symposium on Fault-Tolerant Computing, pp. 164-169, June 1988.
74. J. S. Upadhyaya and K. K. Saluja, "An experimental study to determine task size for rollback recovery systems," IEEE Transactions on Computers, vol. 37, pp. 872-877, July 1988.
75. S. M. Reddy, K. K. Saluja, and M. G. Karpovsky, "A data compression technique for built-in self-test," IEEE Transactions on Computers, vol. 37, pp. 1151-1156, September 1988. (also correction to the paper in IEEE Transactions on Computers , Vol. 38, No. 2, February, 1989, pp. 320.)
76. G. L. Craig, C. R. Kime, and K. K. Saluja, "Test scheduling and control for VLSI built-in self-test," IEEE Transactions on Computers, vol. 37, pp. 1099-1109, September 1988.
77. K. K. Saluja, R. Sharma, and C. R. Kime, "A concurrent testing technique for digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, pp. 1250-1260, December 1988.
78. K. K. Saluja, FTCS 19 to feature sessions on fault-tolerant computing from industrial perspective, IEEE Computer, p. 110, May 1989.
79. M. Franklin, K. K. Saluja, and K. Kinoshita, & quot;Row/column pattern sensitive fault detection in RAMs via built-in self-test," Digest International Symposium on Fault Tolerant Computing, pp. 36-43, June 1989.
80. G. S. Sohi, M. Franklin, and K. K. Saluja, "A study of time-redundant fault tolerant techniques for high-performance pipelined computers," Digest International Symposium on Fault Tolerant Computing, pp. 436-443, June 1989. M. Franklin,
81. K. K. Saluja, and K. Kinoshita, "Design of a BIST RAM with row/column pattern sensitive fault detection capability," Proceedings of the International Test Conference, pp. 327-336, August 1989.
82. K. K. Saluja and S. M. Reddy, Fault-tolerance is apt to be vital feature of future computers, keynoter tells symposium, IEEE Computer, pp. 106-107, September 1989.
83. T. P. Kelsey and K. K. Saluja, "Fast test generation for sequential circuits," Proc. IEEE International Conference on Computer Aided Design, pp. 354-357, November 1989.
84. K. K. Saluja, Test generation for sequential circuits, IEEE FALLCON'89, Cedar Rapids, Iowa, 1989. (Invited paper.)

1990-1999

85. S. Upadhyaya, H. Pham, and K. K. Saluja, "Reliability enhancement by submodule redundancy," Annual Reliability and Maintainability Symposium, January 1990.
86. K. C. Cheung, G. S. Sohi, K. K. Saluja, and D. K. Pradhan, "Design and analysis of a gracefully-degrading interleaved memory system," IEEE Transactions on Computers, vol. 39, pp. 63-71, January 1990.
87. M. Franklin, K. K. Saluja, and K. Kinoshita, "A built-in self-test algorithm for row/column pattern sensitive faults in RAMs," IEEE Journal of Solid-State Circuits, vol. 25, pp. 514-524, April 1990.
88. K. K. Saluja and K. Kim, "Improved test generation for high activity circuits,"IEEE Design and Test of Computers, vol. 7, pp. 26-31, August 1990.
89. M. Franklin and K. K. Saluja, "Built-in self-testing of random access memories," IEEE Computer, vol. 23, pp. 45-56, October 1990.
90. K. Akiyama and K. K. Saluja, "A method of reducing aliasing in a built-in self-test environment," IEEE Trans. on Computer-Aided Design, vol. 10, pp. 548-553, April 1991.
91. M. Franklin and K. K. Saluja, "Pattern sensitive fault testing of RAMs with built-in ECC," Digest International Symposium on Fault Tolerant Computing, pp. 385-392, June 1991.
92. M. Franklin and K. K. Saluja, "An algorithm to test RAMs for physical neighborhood pattern sensitive faults," Proceedings of the International Test Conference, pp. 674-684, October 1991.
93. C. F. See and K. K. Saluja, "An efficient method for computation of signatures," The Fifth International Conference on VLSI Design, pp. 245-250, January 1992.
94. J. Beetem, D. Dietmeyer, Y. Hu, R. J. C. Kime, P. Ramanathan, and K. Saluja, "Design automation research at the University of Wisconsin-Madison," SIGDA Newsletter, vol. 21, March 1992.
95. P. Ramanathan, K. K. Saluja, and M. Franklin, "Zero cost testing of check bits in RAMs with on-chip ECC," IEEE VLSI Test Symposium, pp. 292-297, April 1992.
96. K. Kim and K. K. Saluja, "On fault detection problem in concurrent fault simulation in synchronous sequential circuits," IEEE VLSI Test Symposium, pp. 125-130, April 1992.
97. K. K. Saluja, C.-Y. Liu, and S. M. Reddy, "On detection of bridging faults in programmable logic arrays," Electronics Letters, vol. 28, pp. 1226-1228, June 1992.
98. A. Majumdar, K. K. Saluja, and R. Jain, "Incorporating testability consideration in high-level synthesis," Digest International Symposium on Fault Tolerant Computing, pp. 272-279, July 1992.
99. K. Kim and K. K. Saluja, "Reducion of dynamic memory usage in concurrent fault simulation for synchrounous sequential circuits," Proceedings of the First Asian Test Symposium, pp. 40-45, November 1992.
100. S. Y. Lee and K. K. Saluja, "An algorithm to reduce test application time in full scan designs," Proc. IEEE International Conference on Computer Aided Design, pp. 17-20, November 1992.
101. K. K. Saluja and C. F. See, "An efficient signature computation method," IEEE Design and Test of Computers, vol. 9, pp. 22-26, December 1992.
102. C. Y. Liu and K. K. Saluja, "Built-in self-test techniques for programmable logic arrays," in VLSI Fault Modeling and Testing Techniques, G. W. Zobrist, editor, pp. 90-122, Ed., Ablex Publishing Corporation, Norwood, NJ, 1993.
103. R. Sharma and K. K. Saluja, "Theory, analysis and implementation of an on-line bist technique," VLSI Design, vol. 1, no. 1, pp. 9-22, 1993. (Invited paper)
104. V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A tutorial on built-in self-test part 1: Principles," IEEE Design and Test of Computers, vol. 10, pp. 73-82, March 1993.
105. K. Kim and K. K. Saluja, "CCSTG: An efficient test pattern generator for sequential circuits," IEEE VLSI Test Symposium, pp. 79-84, April 1993.
106. S. Y. Lee and K. K. Saluja, "Efficient test vectors for ISCAS sequential benchmark circuits," International Symposium on Circuits and Systems, pp. 1511-1514, May 1993.
107. V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A tutorial on built-in self-test part 2: Applications," IEEE Design and Test of Computers, vol. 10, pp. 69-77, June 1993.
108. M. Franklin and K. K. Saluja, "Theory and techniques for testing check-bits in RAMs with on-chip ECC," IEICE Transactions on Information and Systems, vol. E76-D, pp. 1243-1252, October 1993.
109. T. P. Kelsey, K. K. Saluja, and S. Y. Lee, "An efficient algorithm for sequential circuit test generation," IEEE Transactions on Computers, vol. 42, pp. 1361-1371, November 1993.
110. P. Ramanathan, K. K. Saluja, and M. Franklin, "Testing check bits at no cost in RAMs with on-chip ECC," IEE Proceedings Part E, vol. 140, pp. 304-312, November 1993.
111. C. Y. Liu and K. K. Saluja, "An efficient algorithm for bipartite PLA folding," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1839-1847, December 1993.
112. B. Narendran, M. Franklin, and K. K. Saluja, "Parallel computation of LFSR signatures," IEEE Second Asian Test Symposium, pp. 75-80, November 1993.
113. R. Chou, K. K. Saluja, and V. D. Agrawal, "Power constraints scheduling of tests," International Conference on VLSI Design, pp. 271-274, January 1994.
114. M. Franklin and K. K. Saluja, "An algorithm to test reconfigured RAMs," International Conference on VLSI Design, pp. 359-364, January 1994. (Honorable Mention Award)
115. A. Mujumdar, R. Jain, and K. K. Saluja, "Incorporating testability considerations in high-level synthesis," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 5, pp. 43-55, February 1994.
116. S. Y. Lee and K. K. Saluja, "Sequential generation of tests with reduced clocks for partial scan designs," IEEE VLSI Test Symposium, pp. 220-225, April 1994.
117. M. Franklin and K. K. Saluja, "Hypergraph coloring and reconfigured RAM testing," IEEE Transactions on Computers, vol. 43, pp. 725-736, June 1994.
118. A. Majumdar, R. Jain, and K. K. Saluja, "Behavioral synthesis of testable designs," Digest International Symposium on Fault Tolerant Computing, pp. 436-445, June 1994.
119. K. K. Saluja, Do we still need research on memory test algorithms, International Workshop on Memory Technology, Design and Testing, p. 64, August 1994. (Panelist.)
120. C.-Y. Liu and K. K. Saluja, "Testable synthesis and testing of finite state machines," IEEE The Third Asian Test Symposium, pp. 305-310, November 1994.
121. K. K. Saluja, "On-chip testing of random access memories," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 5, pp. 367-376, December 1994. (Invited paper)
122. M. Franklin, K. K. Saluja, and K. Kim, "Fast computation of MISR signatures," International Conference on VLSI Design, January 1995.
123. H. Zheng, K. K. Saluja, and R. Jain, "Test application time reduction for scan based sequential circuits," Proceedings 5th Great Lake Symposium on VLSI, pp. 188-191, March 1995.
124. T.-Y. Kuo, K. K. Saluja, and C.-Y. Liu, "An optimized testable architecture for FSMs," IEEE VLSI Test Symposium, pp. 164-169, April - May 1995.
125. N. Jiang, R. Chou, and K. K. Saluja, "Synthesizing finite state machines for minimum length synchronizing sequence using partial reset," International Symposium on Fault Tolerant Computing, pp. 41-49, June 1995.
126. M. Franklin and K. K. Saluja, "Embedded RAM testing," International Workshop on Memory Technology, Design and Testing, August 1995. (Invited Paper.)
127. M. T.-Y. Kuo and K. K. Saluja, "High-level synthesis of testable ASIC designs," ASP_DAC 95/CHDL 95/VLSI 95 Tutorials - Tutorial D, pp. 53-151, August 1995. (Invited Paper.)
128. S. Y. Lee and K. K. Saluja, "Test application time reduction for sequential circuits with scan," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, pp. 1128-1140, September 1995.
129. T. Lambert and K. K. Saluja, "Methods for dynamic test vector compaction in sequential test generation," International Conference on VLSI Design, pp. 166-169, January 1996.
130. L. Nachman, K. K. Saluja, S. Upadhyaya, and R. Reuse, "Random pattern testing of sequential circuits revisited," International Symposium on Fault Tolerant Computing, pp. 44-52, June 1996.
131. W. Xiaoqing, K. K. Saluja, K. Kinoshita, and H. Tamamoto, "Transistor leakage fault location for static CMOS circuits," International Workshop Computer-Aided Design, Test and Evaluation for Dependability (CADTED), pp. 297-302, July 1996.
132. K. K. Saluja, R. Chou, W. Xiaoqing, and L. Nachman, "Synthesis, testing and diagnosis of faults in digital circuits," International Workshop Computer-Aided Design, Test and Evaluation for Dependability (CADTED), pp. 236-245, July 1996. (Invited Paper.)
133. K. Kim and K. K. Saluja, "HYSIM: Hybrid fault simulator for synchronous sequential circuits," VLSI Design, vol. 4, pp. 181-197, August 1996.
134. M. Franklin and K. K. Saluja, "Testing reconfigured RAMs and scrambled address RAMs for pattern sensitive faults," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 1081-1087, September 1996.
135. A. Mujumdar, R. Jain, and K. K. Saluja, "A testability and performance driven solution to the binding problem," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 1212-1225, October 1996.
136. W. Xiaoqing, K. K. Saluja, K. Kinoshita, and H. Tamamoto, "Equivalence fault collapsing for transistor leakage faults," IEEE International Workshop on Iddq Testing, pp. 79-83, October 1996.
137. W. Xiaoqing and K. K. Saluja, "A new method towards achieving global optimality in technology mapping," Proc. IEEE International Conference on Computer Aided Design, pp. 9-12, November 1996.
138. R. Chou and K. K. Saluja, "Sequential circuit testing: From DFT to SFT," International Conference on VLSI Design, pp. 274-278, January 1997.
139. R. M. Chou, K. K. Saluja, and V. D. Agrawal, "Scheduling tests for VLSI systems under power constraints," IEEE Transactions on VLSI Systems, vol. 5, pp. 175-185, June 1997.
140. Y. C. Kim, K. K. Saluja, W. Xiaoqing, and B. Vinnakota, "On Iddq testing of CMOS circuits for stuck-open faults," IASTED International Conference on Modeling, Simulation and Optimization, pp. 347-352, August 1997. (Invited Paper)
141. W. Xiaoqing, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "A method for transistor short fault diagnosis in CMOS circuits," Japanese Fault Tolerant Computing Workshop, August 1997. (In Japanese)
142. W. Xiaoqing, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Fault diagnosis for static CMOS circuits," IEEE The Sixth Asian Test Symposium, November 1997.
143. S. Kajihara and K. K. Saluja, "On test pattern compaction using random pattern fault simulation," International Conference on VLSI Design, pp. 464-469, January 1998.
144. L. Nachman, K. K. Saluja, S. Upadhyaya, and R. Reuse, "A novel approach to random pattern testing of sequential circuits," IEEE Transactions on Computers (Special Issue on Dependability of Computing Systems), vol. C-47, pp. 129-134, January 1998.
145. W. Xiaoqing, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Transistor leakage fault diagnosis with Iddq and logic information," IEICE Transactions on Information and Systems, vol. E81-D, pp. 372-381, April 1998.
146. W. Xiaoqing, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Transistor leakage fault diagnosis for CMOS circuits," IEICE Transactions on Information and Systems (Special issue on Test and Diagnosis of VLSI), vol. E81-D, pp. 697-705, July 1998.
147. K. T. Le and K. K. Saluja, "A heuristic measure to maximize detected faults per test," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 13, pp. 57-60, August 1998.
148. Y. Higami, K. K. Saluja, and K. Kinoshita, "Static test compaction for IDDQ testing of sequential circuits," IEEE International Workshop on Iddq Testing, November 1998.
149. W. Xiaoqing, T. Honzawa, H. Tamamoto, K. K. Saluja, and K. Kinoshita, "Design for diagnosability of CMOS circuits," IEEE The Seventh Asian Test Symposium, December 1998.
150. Y. Higami, K. K. Saluja, and K. Kinoshita, "Observation time reduction for IDDQ testing of bridging faults in sequential circuits," IEEE The Seventh Asian Test Symposium, December 1998.
151. Y. Kim and K. K. Saluja, "Sequential test generation: Past, present and future," Integration - The VLSI Journal, vol. 26, pp. 41-54, December 1998.
152. Y. Higami, K. K. Saluja, and K. Kinoshita, "Efficient techniques for reducing IDDQ observation time for sequential circuits," International Conference on VLSI Design, pp. 72-77, January 1999.
153. Y. C. Kim, V. Agrawal, and K. K. Saluja, "A correlation matrix method of clock partitioning for sequential circuit testability," Ninth Great Lakes Symposium on VLSI, pp. 300-303, March 1999.
154. H. Wada, T. Masuzawa, K. K. Saluja, and H. Fujiwara, "A DFT method for RTL data paths achieving 100% fault efficiency under hierarchical test environment," Eutopian Test Workshop, May 1999.
155. Y. Higami, K. K. Saluja, Y. Takamatsu, and K. Kinoshita, "Static test compaction for IDDQ testing of bridging faults in sequential circuits," IEICE Transactions on Information and Systems, vol. J82-D-I, pp. 879-887, July 1999. (in Japanese)
156. H. Wada, T. Masuzawa, K. K. Saluja, and H. Fujiwara, "A non-scan dft method for data paths to provide complete fault efficiency," Transactions of IEICE (DI), vol. J82-D-I, pp. 843-851, July 1999. (in Japanese)
157. Y. Higami, K. K. Saluja, Y. Takamatsu, and K. Kinoshita, "Fault simulation techniques to reduce iddq measurement vectors for sequential circuits," IEEE The Eighth Asian Test Symposium, pp. 141-146, December 1999.

2000-2009

158. M. Mohammad, K. K. Saluja, and A. Yap, "Testing flash memories," International Conference on VLSI Design, pp. 406-411, January 2000. (The Silver Quill from Motorola and Candidate for Best paper Award at VLSI Design Conference )
159. H. Wada, T. Masuzawa, K. K. Saluja, and H. Fujiwara, "Design for strong testability of RTL data paths to provide complete fault efficiency," International Conference on VLSI Design, pp. 300-305, January 2000.
160. Y. C. Kim, V. Agrawal, and K. K. Saluja, "On guranteed combinational atpg for non-scan and partial scan sequential circuits," International Test Synthesis Workshop, March 2000.
161. Y. Higami, Y. Takamatsu, K. K. Saluja, and K. Kinoshita, "Algorithms to select IDDQ measurement vectors for bridging faults in sequential circuits," , vol. 16, pp. 443-451, Oct 2000.
162. F. Rashid, K. K. Saluja, and P. Ramanathan, "Fault tolerance through re-execution in multiscalar architecture," International Conference on Dependable Systems and Networks, Also FTCS-30, pp. 482-491, June 2000.
163. Y. Kim, K. K. Saluja, and V. D. Agrawal, "Combinational test generation for acyclic sequential circuits using a balanced atpg model," International Conference on VLSI Design, pp. 143-148, January 2001. ( Best Student Paper Award)
164. O. Ercevik, T. Clouqueur, H. Takahashi, and K. K. Saluja, "Efficient signature-based fault diagnosis using variable size windows," International Conference on VLSI Design, pp. 391-396, January 2001.
165. R. M. Chou, , and K. K. Saluja, "Testable sequential circuit design: A partition and resynthesis approach," IEEE VLSI Test Symposium, pp. 62-67, April - May 2001.
166. M. G. Mohammad and K. K. Saluja, "Flash memory disturbances; modeling and test," IEEE VLSI Test Symposium, pp. 218-224, April - May 2001.
167. H. Takahashi, D. Kadoguchi, K. O. Boateng, Y. Takamatsu, and K. K. Saluja "Design error diagnosis using backward path-tracing and logic simulation," International Technical Conference on Circuits/System, Computers and Communications (ITC-CSCC 01) , pp.~426--429, July 2001
168. M. G. Mohammad, K. K. Saluja, and A. Yap, "Disturbance models and test procedures for flash memories," Journal of Electronic Testing: Theory and Applications (JETTA), vol. , no. 6, pp.495-508, Oct 2001.
169. Y. C. Kim, V. D. Agrawal and K. K. Saluja, "Combinational Test Generation for Various Classes of Acyclic Sequential Circuits," Proc. of the International Test Conference, pp. 1078-1087, Oct., 2001.
170. K. Keller, K. K. Saluja, H. Takahashi, and Y. Takamatsu, "On Reducing the Target Fault List of Crosstalk-Induced Delay Faults in Synchronous Sequential Circuits", Proc. of the International Testing Conference, pp. 568-577, Oct., 2001
171. H. Takahashi, M. Phadoongsidhi, Y. Higami, K. K. Saluja, and Y. Takamatsu, "Simulation-based Diagnosis for Crosstalk Faults in Sequential Circuits," Asian Test Symposium, pp. 63-68, Nov. 2001
172. Y. C. Kim, V. D. Agrawal, and K. K. Saluja, "Multiple Faults: Modeling, Simulation and Test," International Conference on VLSI Design (also Asia and South Pacific Design Automation Conference), pp. 592-597, Jan. 2002.
173. E. F. Weglarz, K. K. Saluja and M. H. Lipasti, "Minimizing Energy Consumption for High-Performance Processing", International Conference on VLSI Design (also Asia and South Pacific Design Automation Conference), pp. 199-204, Jan. 2002.
174. F. Li, L. He and Kewal K. Saluja "Estimation of Maximum Power-up Current", International Conference on VLSI Design (also Asia and South Pacific Design Automation Conference), pp. 51-56, Jan. 2002.
175. H. Takahashi, M. Phadoongsidhi, Y. Higami, K. K. Saluja, and Y. Takamatsu, "Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation," IEICE Trans., vol. E00-A, no. 1., pp. 1515-1525, Jan. 2002
176. H. Takahashi, K.~O. Boateng, K. K. Saluja, and Y. Takamatsu, "On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 21, pp. 362-368, March 2002
177. P. Ramanathan, K.-C. Wang, K. K. Saluja, and T. Clouqueue,"Communication support for location-centric collaborative signal processing in sensor networks," Proceedings of {DIMACS} Workshop on Pervasive Networks, May 2002.
178. T. Clouqueue, V. Phipathanasuphorn, P. Ramanathan, and K. K. Saluja,"Sensor deployment strategy for target detection," First ACM International Workshop on Wireless Sensor Networks and Applications, pp. 42-48, September 2002.
179. M. Phadoonsidhi, K.T. Le, and K. K. Saluja, "A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits," IEEE The Eleventh Asian Test Symposium, pp. 182-187, November 2002.
180. K. J. Keller, H. Takahashi, K. T. Le, K. K. Saluja, and Y. Takamatsu,"Reduction of target fault list for crosstalk-induced delay faults by using layout constraints," IEEE The Eleventh Asian Test Symposium, pp. 242-247, November 2002.
Hu,"Collaborative sensor signal processing for target detection, localization, and tracking," 23rd Army Science Conference, December 2002.
181. H. Takahashi, K. K. Saluja, and Y. Takamatsu,"An alternative method of generating tests for path delay faults using $n_i$-detection test sets," IEEE 2002 Pacific Rim International Symposium on Dependable Computing (PRDC02), pp. 275-282, December 2002.
182. V.D. Agrawal, D. H. Baik, Y. C. Kim and K. K. Saluja, "Exclusive Test and the Applications to Diagnosis," International Conference on VLSI Design,pp. 143-148, January 2003.
183. M. G. Mohammad and K. K. Saluja, "Electrical model for program disturb faults in non-volatile memories," International Conference on VLSI Design, pp. 217-222, January 2003.
184. K. K. Saluja," Research directions in manufacturing tests of nanotechnology products," 2003 NAIST COE International Symposium - Ubiquitous Networked Media Computing, pp. 237-255, March 2003.
185. T. Clouqueur, P. Ramanathan and K. K. Saluja,"Exposure of variable speed targets through a sensor field," FUSION: Sixth International Conference on Information Fusion, pp. 599-607, July 2003.
186. T. Clouqueue, V. Phipathanasuphorn, P. Ramanathan, and Kewal K. Saluja, "Sensor deployment strategy for detection of targets traversing a region," ACM Mobile Networks and Applications , vol. 8, pp. 453-461, August 2003.
187. M. G. Mohammad and K. K. Saluja, "Simulating program disturb faults in flash memories using SPICE compatible electrical model," IEEE Transactions on Electron Devices , vol. 50, pp. 2286--2291, October 2003.
188. M. Phadoongsidhi and K. K. Saluja, "Event-centric simulation of crosstalk pulse faults in sequential circuits," IEEE International Conference on Computer Design (ICCD), pp. 42-47, October 2003.
189. K. K. Saluja,"Outstanding challenges in testing nanotechnology based integrated circuits," IEEE The Twelfth Asian Test Symposium (Keynote address), pp. 1-2, November 2003.
190. M. G. Mohammad and K. K. Saluja, "Stress test for disturb faults in non-volatile memories," IEEE The Twelfth Asian Test Symposium , pp. 384-387, November 2003.
191. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara,"Software-based delay fault testing of processor cores," IEEE The Twelfth Asian Test Symposium , pp. 68-71, November 2003.
192. X. Wen, H. Tamamoto, K. K. Saluja, and K. Kinoshita,"Fault diagnosis for physical defects of unknown behaviors," IEEE The Twelfth Asian Test Symposium , pp. 236-241, November 2003.
193. H. Takahashi, K. K. Saluja, and Y. Takamatsu, "An alternative test generation for path delay faults by using ni-detection test sets," Transactions of IEICE (ECO-A) (Special issue on Dependable Computing} , vol. E86-D, pp. 2650--2658, December 2003.
194. M. Phadoongsidhi and K. K. Saluja," Static timing analysis of irreversible crosstalk noise pulse faults," (Best student paper award), International Conference on VLSI Design, pp. 437-442, January 2004.
195. D. Baik, S. Kajihara, and K. K. Saluja," Random access scan: A solution to test power, test data volume and test time," International Conference on VLSI Design, pp. 883-889, January 2004.
196. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara," Instruction-based delay fault self-testing of processor cores," International Conference on VLSI Design, pp. 933-938, January 2004.
197. T. Clouqueue, Kewal K. Saluja and P. Ramanathan, "Fault tolerance in collaborative sensor networks for target detection," IEEE Transactions on Computers , vol. 53, pp. 320--333, March 2004.
198. S. Kajihara, K. K. Saluja and S. M. Reddy," Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values," Eutopian Test Symposium, pp. 108-113, May 2004.
199. E.~F. Weglarz, K. K. Saluja, and T. M. Mak," Testing of hard faults in simultaneous multithreaded processors," Internaltional On-Line Test Symposium, pp. 94-100, June 2004.
200. M. L. King and K. K. Saluja," Testing micropipelined asynchronous circuits," Proceedings of the International Test Conference, pp. 329-338, October 2004.
201. J. Tsai, D. Baik, C. C. Chen, and K. K. Saluja," A yield improvement methodology using pre- and post-silicon statistical clock scheduling," Proceedings of the IEEE International Conference on Computer Aided Design, pp. 611-618, November 2004.
202. W. Xiaoqing, H. Tamamoto, and K. K. Saluja," On per-test fault diagnosis using x-fault model," Proceedings of the IEEE International Conference on Computer Aided Design, pp. 633-640, November 2004.
203. J. Tsai, D. Baik, C. C. Chen, and K. K. Saluja," False path and clock scheduling based yield-aware gate sizing," International Conference on VLSI Design, pp. 423-426, January 2005.
204. M. Phadoongsidhi and K. K. Saluja,"SCINDY: Logic crosstalk delay fault simulation in sequential circuits," International Conference on VLSI Design, pp. 820-823, January 2005.
205. H. Takahashi, K. J. Keller, K. T. Le, K. K. Saluja, and Y. Takamatsu, "A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits,"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, pp. 252--263, Feb 2005.
206. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara, "Delay fault testing of processor cores in functional mode," IEICE Transactions on Information and Systems , vol. E88-D, pp. 610-618, March 2005.
207. X. Wen, S. Kajihara, H. Tamamoto, K. K. Saluja and K. Kinoshita,"On design for Iddq based diagnosis of CMOS circuits using multiple power supplies," IEICE Transactions on Information and Systems, pp. 703--710, April 2005.
208. X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja and K. Kinoshita,"On low-capture-power test generation for scan testing," IEEE VLSI Test Symposium, pp. 265--270, May 2005.
209. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara,"Instruction-based delay fault self-testing of pipelined processor cores," IEEE International Symposoum on Circuits and Systems (ISCAS), pp. 5686--5689, May 2005.
210. V. Singh, M. Inoue, K. K. Saluja, and H. Fujiwara,"Program-based testing of super-scalar microprocessors," IEEE North Atlantic Test Workshop, pp. 79--86, May 2005.
211. Y. Kim, K. K. Saluja, and V. D. Agrawal, "Combinational automatic test pattern generation for acyclic sequential circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 24, pp. 948--956, May 2005.
212. J.-L. Tsai, D. Baik, C. C.-P. Chen, and K. K. Saluja, " Yield-driven false-path-aware clcok-skew scheduling, " IEEE Design and Test of Computers, vol. 22, pp. 214--222, May-June 2005.
213. M. G. Mohammad and K. K. Saluja, "Optimizing program disturb fault tests using defect-based testing " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 24, pp. 905--915, June 2005.
214. T. Clouqueur, K. K. Saluja, and H. Fujiwara, "Matrices of multiple weights for test response compaction with unknown values, " IEEE 6rd Workshop on RTL and High Level Testing, July 2005.
215. Y. Nakamura, T. Clouqueur, K. K. Saluja, and H. Fujiwara, " Perfect error identification in at-speed bist environment, " IEEE 6rd Workshop on RTL and High Level Testing, July 2005.
216. M. Nakazato, S. Ohtake, K. K. Saluja, and H. Fujiwara, " Acceleration of test generation for sequential circuits using knowledge obtained from synthesis for testability, " IEEE 6rd Workshop on RTL and High Level Testing, July 2005. (Best paper award)
217. T. Clouqueur, K. Zarrineh, K. K. Saluja, and H. Fujiwara, " Design and analysis of multiple weight compactors of responses containing unknown values, " Proceedings of the International Test Conference, pp. 1099--1108, October 2005.
218. D. Baik and K. K. Saluja, " Progressive random access scan: A simultaneous solution to test power, test data volume and test time, " Proceedings of the International Test Conference, pp. 359--368, October 2005.
219. X. Wen, Y. Yamashita, S. Kajihara, L.-T. Wang, K. K. Saluja, and K.~Kinoshita, " Low-capture-power test generation for at-speed scan testing, " Proceedings of the International Test Conference, pp. 1019--1028, October 2005.
220. T. Chin, P. Ramanathan, and K. K. Saluja, " Exposure for collaborative detection using mobile sensor networks, " IEEE International Conference on Mobile Ad-Hoc and Sensor Systems, pp. 743--750, October 2005.
221. D. Baik and K. K. Saluja, " State-reuse test generation for progressive random access scan: Solution to test power, application time and data size, " IEEE The Fourteenth Asian Test Symposium, pp. 272--277, November 2005.
222. T. Clouqueur, K. K. Saluja, and H. Fujiwara " A class of linear space compactors for enhanced diagnostic, " IEEE The Fourteenth Asian Test Symposium, pp. 260--265, November 2005.
223. X. Wen, T. Suzuki, S. Kajihara, K. Miyase, Y. Minamoto, L.-T. Wang, and K. K. Saluja, " Efficient test set modification for capture power reduction, " Journal of Low Power Electronics, vol. 1, pp. 319--330, December 2005.
224. D. Baik and K. K. Saluja,"Test cost reduction using partitioned grid random access scan," International Conference on VLSI Design, paper 1D.3, January 2006.
225. X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. K. Saluja, L.-T. Wang, K. S. Abdel-Hazer, and K. Kinoshita, " A new ATPG method for efficient capture power reduction during scan testing, " VLSI Test Symposium, pp. 58--65, March 2006.
226. T. Chin, P. Ramanathan, and K. K. Saluja, " Analytic modeling of detection atency in mobile sensor networks, " ACM International Conference on Information Processing in Sensor Networks (ISPN06), pp. 194--201, April 2006.
227. T. Clouqueur, K. Zirrineh, K. K. Saluja, and H. Fujiwara, " Diagnosis in designs with block compactors, " IEEE European Test Symposium, May 2006.
228. X. Wen, K. Miyase, T. Suzuki, Y. Yamata, S. Kajihara, L.-T. Wang, and K. K. Saluja, " A highly-guided x-filling method for effective low-capture-power scan test generation, " International Conference on Computer Design (ICCD), pp. 251--258, October 2006.
229. X. Wen, Y. Yamato, K. Miyase, S. Kajihara, H. Furukawa, L.-T. Wang, K. K. Saluja, and K. Kinoshita, " An improved method of per-test x-fault diagnosis for deep-submicron LSI circuits, " IEEE7th Workshop on RTL and High Level Testing, November 2006. (Best paper award)
230. Y. Nakamura, T. Clouqueur, K. K. Saluja, and H. Fujiwara, " Diagnosing at-speed scan bist circuits using a low speed and low memory tester, " IEEE The Fifteenth Asian Test Symposium, pp. 409--414, November 2006.
231. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu, " Diagnosis of transistor shorts in logic test environment, " IEEE The Fifteenth Asian Test Symposium, pp. 354--359, November 2006.
232. X. Wen, Y. Yamato, K. Miyase, S. Kajihara, H. Furukawa, L.-T. Wang, K. K. Saluja, and K. Kinoshita, "An improved method of per-test x-fault diagnosis for deep-submicron LSI circuits, " IEEE 7th Workshop on RTL and High Level Testing, November 2006.
233. X. Wen, S. Kajihara, K. Miyase, Y. Yamato, K. K. Saluja, L.-T. Wang, and K. Kinoshita " A per-test fault diagnosis method based on the x-fault model, " IEICE Transactions on Information and Systems, vol. E89-D, pp. 2756--276, November 2006.
234. T. Chin, P. Ramanathan, and K. K. Saluja, " Optimal sensor distribution for maximum exposure in a region with obstacles, " IEEE Globecom Technical Conference (GLOBECOM2006), pp. WSN19--3:1--5, November-December 2006.
235. E. Weglarz, K. K. Saluja and M. Lipasti, " Energy estimation of the memory subsystem in mutiprocessor systems, " Journal of Low Power Electronics, vol. 2, pp. 325--332, December 2006.
236. K. T. Le, D. Baik, and K. K. Saluja," Test time reduction to test for path-delay faults using enhanced random access scan," International Conference on VLSI Design, pp. 769-774, January 2007.
237. Y. Higami, K. K. Saluja, H. Takahashi, and Y. Takamatsu," Fault coverage and fault efficiency of transisor shorts using gate-level simulation and test generation," International Conference on VLSI Design, pp. 781-786, January 2007.
238. X. Yang, E. Weglarz, and K. K. Saluja," On NBTI degradation process in digital logic circuits enhanced random access scan," International Conference on VLSI Design, pp. 723-728, January 2007.
239. M. Nakazato, S. Ohtake, K. K. Saluja, and H. Fujiwara " Accelration of test generation for sequential circuits using knowledge obtained from synthesis for testability, " IEICE Transactions on Information and Systems, vol. E90-D, pp. 296--305, January 2007.
240. X. Yang and K. K. Saluja," Combating NBTI degradation via gate sizing," International Symposium on Quality Elecronic Desing (ISQED), pp. 47-52, March 2007.
241. N. Aggarwal, P. Ranganathan, N. P.Jouppi, J. E. Smith, K. K. Saluja, and G. Krejci," Motivating commodity multi-core processor design for system-level error protection," IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE-03), April 2007.
242. W. Xiaoqing, K. Miyase, T. Suzuki, S. Kajihara, Y. Ohsumi, and K. K. Saluja," Critical-path-aware x-filling for effective IR-drop reduction in at-speed scan testing," International Design Automation Conference (DAC), pp. 527-532, June 2007.
243. Y. Nakamura, T. Clouqueur, K. K. Saluja, and H. Fujiwara," Diagnosing at-speed scan BIST circuits using a low speed and low memory tester," IEEE Transactions on Very Large Scale Integrated Systems, vol. 15, pp. 790--800, July 2007.
244. X. Wen, S. Kajihara, K. Miyase, T. Suzuki, K. K. Saluja, L.-T. Wang, K. S. Abdel-Hafez, and K. Kinoshita, " A novel ATPG method for capture power reduction during scan testing, " IEICE Transactions on Information and Systems, vol. E90-D, pp. 1398--1405, September 2007.
245. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu, " Test generation for transistor shorts using stuck-at fault simulator and test generator, " IEEE The Sixteenth Asian Test Symposium, pp. 271--274, October 2007.
246. K. K. Saluja, S. Vijaykumar, W. Sootkaneung, and X. Yang," NBTI degradation: A problem or a scare?," [PDF] International Conference on VLSI Design, pp. 137-142, January 2008.
247. M. G. Mohammad and K. K. Saluja," [PDF] Testing flash memories for tunnel oxide defects," International Conference on VLSI Design, pp. 157-162, January 2008.
248. C. Wang, P. Ramanathan, and K. K. Saluja "Moments based blind calibration in mobile sensor networks," International Conference on Communications - Signal Processing and Communication (ICC08) , pp. 896-900, May 2008.
249. N. Aggarwal, N. Jouppi, P. Ranganathan, J. E. Smith, and K. K. Saluja "COVERT: Configurable virtual redundancy with transparent availability on commodity software," Proc. ACM 13th Int. Conference on Architecture Support for Programming Language and Operating Systems(ASPLOS-08), March 2008.
250. Y. Higami, K. K. Saluja, H. Takahashi, S.-Y. Kobayashi, and Y. Takamatsu, "Fault simulation and test generation for transistor shorts using stuck-at test tools, "IEICE Transactions on Information and Systems, vol. E91-D, pp. 690--699, March 2008.
251. N. Aggarwal, N. Jouppi, P. Ranganathan, J. E. Smith, and K. K. Saluja "Reducing overhead for soft error coverage in high availability systems," IEEE Workshop on Silicon Errors in Logic-System Effects (SELSE-04), 2008.
252. N. Aggarwal, N. Jouppi, P. Ranganathan, J. E. Smith, and K. K. Saluja"Reducing overhead for soft error coverage in high availability systems," HP Technical ReportC , April 2008.
253. K. Miyase, X. Wen, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja"A capture-safe test generation scheme for at-speed scan testing," European Test Symposium (ETS), pp. 55-60, May 2008.
254. C. Yao and K. K. Saluja"A study of word oriented random access scan based BIST for low area overhead and low power," Workshop on the Impact of Low Power Design on Test and Reliability (LPonTR), May 2008.
255. S. Ohtake and K.~K. Saluja"A systematic scan insertion technique for asynchronous on-chip interconnects," Workshop on the Impact of Low Power Design on Test and Reliability (LPonTR), May 2008.
256. M. G. Mohammad and K. K. Saluja"Analysis and test procedures for {NOR} flash memory defects," Microelectronics Journa, vol. 48, pp. 698-709, May 2008.
257. E. Hill and M. Lipasti and K. K. Saluja "An accurate flip-flop selection technique for reducing logic SER," International Conference on Dependable Systems and Networks , pp. 128-136, June 2008.
258. C. Wang, P. Ramanathan, and K. K. Saluja "Calibrating non-linear mobile sensors," IEEE Communication Society Conference on Sensor, Mesh, and Ad-Hoc Communications and networks (SECON-08), pp. 533-541, June 2008.
259. X. Wen, K. Miyase, T. Suzuki, S. Kajihara, L.-T. Wang, K. K. Saluja, and K. Kinoshita"Low-capture-switching-activity test generation for reducing IR-drop in at-speed scan testing," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 24, pp. 379-391, August 2008.
260. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu " Increasing defect coverage by generating test vectors for stuck-open faults," EEE The Seventeenth Asian Test Symposium , pp. 97-102, November 2008.
261. N. Aggarwal, N. P. Jouppi, P. Ranganathan, J. E. Smith, and K. K. Saluja "Implementing high availability memory with a duplicated cache," IEEE/ACM International Symposium on Microarchitecture (MICRO-41) , 2008.
262. Y. Higami, K. K. Saluja, H. Takahashi, S.-Y. Kobayashi, and Y. Takamatsu, "Maximizing stuck-open fault coverage using stuck-at test vectors, "IEICE Transaction Fundamentals, vol. E91-A, pp. 3506--3513, December 2008.
263. C. Yao, K. K. Saluja, and A. SinkarAuthors "WOR-BIST: A complete test solution for designs meeting power, area and performance requirements," International Conference on VLSI Design , pp. 479-484, January 2009.
264. L. Xie, A. Davoodi, K. K. Saluja, and A. Sinkar "False path aware timing-yield estimation under variability," VLSI Test Symposium , pp. 161-166, April 2009.
265. R. C. Jumani, N. B. Jain, V. Singh, and K. K. Saluja "DX-Compactor:Distributed x-compaction for SoCs," The Nineteenth Great Lake Symposium on VLSI (GLSVLSI), pp. 505-510, May 2009.
266. T.-L. Chin, P. Ramanathan, and K. K. Saluja "Modeling detection latency with collaborative mobile sensing architecture," IEEE Transactions on Computers, vol. 58, pp. 692-705, May 2009.
267. C. Wang, P. Ramanathan, and K. K. Saluja"Blindly calibrating mobile sensors using piecewise linear functions," IEEE Communication Society Conference on Sensor, Mesh, and Ad-Hoc Communications and networks (SECON-09), pp. 1-9, June 2009.
268. P. Subramanyan, V. Singh, K. K. Saluja, and E. Larsson"Power efficient redundant execution for chip microprocessors," Third Workshop on Dependable and Secure Nanocomputing (WDSN-09), pp. 3.3.0-3.3.5, June 2009.
269. C. Yao, K. K. Saluja, and P. Ramanathan"Power and thermal constraint test scheduling," Proceedings of the International Test Conference, pp. PO.6.0-PO6.1, November 2009.
270. C. Yao, K. K. Saluja, and P. Ramanathan"Partition based SoC test scheduling with thermal and power constraints under deep submicron technologies," IEEE The Eighteenth Asian Test Symposium , pp. 285-290, November 2009.
271. C. Yao, K. K. Saluja, and P. Ramanathan"Thermal and power constrained test scheduling with adaptive cooling periods," ECE0902 Technical Report , August 2009.
272. K. Kim and K. K. Saluja"Low-area wrapper cell design for hierarchical SoC testing," Journal of Electronic Testing: Theory and Applications (JETTA), vol. 25, pp. 347--352, December 2009.
273. Y. Higami, K. K. Saluja, H. Takahashi, S.-Y. Kobayashi, and Y. Takamatsu, "Addressing defect coverage through generating test vectors for transistor defects," IEICE Transactions (Special issue on VLSI Design and CAD Algorithms , vol. E92-A, pp. 3128--3135, December 2009.
274. Y. Higami, K. K. Saluja, H. Takahashi, S.-Y. Kobayashi, and Y. Takamatsu "An algorithm for diagnosing transistor shorts using gate-level simulation," IPSJ Transaction on System LSI Design Methodology , vol. 2, pp. 252-262, 2009.

2010-

275. R. Adiga, A. Gandhi, V. Singh, K. Saluja, H. Fujiwara, and A. Singh"On minimization of test application time for RAS," International Conference on VLSI Design, pp. A7.1-A7.6, January 2010.
276. W. Sootkaneung and K. K. Saluja"Sizing techniques for improving soft error immunity in digital circuits," International Conference on VLSI Design and Communication Systems, pp. 87-92, January 2010.
277. P. Subramanyan, V. Singh, K. K. Saluja, and E. Larsson "Mulitplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors," International Conference on Design and Test in Europe (DATE-10), pp. 1572-1577, March 2010.
278. Warin Sootkaneung and Kewal K Saluja "Gate Input Reconfiguration for Combating Soft Errors in Combinational Circuits," Workshop on Dependable and Secure Nano-Computing (WDSN), May 2010.
279. A. Abhishek, A. Khan, V. Singh, K. K. Saluja, and A. D. Singh"Test application time minimization for RAS using basis optimization of column decoders," International Symposium on Circuits And Systems , pp. 2614-2617, May 2010.
280. H. Y. Choi and K. K. Saluja"Detection of inter-port bridging faults in dual-port memories," International Symposium on Circuits And Systems , pp. 657-660, May 2010.
281. R. Agida, A. Gandhi, V. Singh, K. K. Saluja, and A. D. Singh"Modified t-flip-flop based scan cell for RAS," Europian Test Symposium (ETS), pp. 113-116, May 2010.
282. P. Subramanyan, V. Singh, and K. K. Saluja"Energy-efficient redundant execution for chip microprocessor," The Twentieth Great Lake Symposium on VLSI (GLSVLSI), pp. 143-146, May 2010.
283. L. Xie, A. Davoodi, and K. K. Saluja"Post-silicon identification of segments on failing speedpaths due to manufacturing variations," International Design Automation Conference (DAC), pp. 274-279, June 2010.
284. P. Subramanyan, V. Singh, K. K. Saluja, and E. Larsson "Energy-efficient fault tolerance in chip multiprocessors using critical value forwarding," International Conference on Dependable Systems and Networks ,pp. 121-130, June 2010.
285. Y.-T. Lin, K. K. Saluja and P. Ramanathan"Connected barrier coverage on a narrow band: Analysis and deployment," IEEE Communication Society Conference on Sensor, Mesh, and Ad-Hoc Communications and networks (SECON-10), pp. 376-384, June 2010.
286. K. Miyase, X. Wen, S. Kajihara, Y. Yamata, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja, "A study of capture-safe test generation flow for at- speed testing," IEICE Transactions on Information and Systems , vol. E93-A, pp. 1309--1318, July 2010.
287. W. Sootkaneung and K. K. Saluja " Optimizing device size for soft error resilience in sub-micron logic circuits," Asian Symposium on Quality Electronic Design (ASQED), pp. 235-242, August 2010.
288. C. Wang, P. Ramanathan, and K. K. Saluja, "Modeling latency - lifetime trade-off for target detection in mobile sensing networks," ACM Transactions on Sensor Networks , Volume 7, pp. 8.1-8.24, August 2010.
289. W. Sootkaneung and K. K. Saluja "On techniques for handling soft errors in digital circuits," Proceedings of the International Test Conference (ITC), pp. 25.2.1-25.2.8, November 2010.
290. T. Chin, P. Ramanathan, and K. K. Saluja, " Collaborative patrolling for target detection using mobile sensor networks, " Proceedings of the IEEE Internatioanl Conference on Wireless Communications and Signal Processing (WCSP), pp. 10.1109.1-10.1109.6, October 2010.
291. H. Yokoyama, K. K. Saluja, and H. Tamamoto "Controlling peak power consumption for scan based multiple weighted random BIST," IEEE The Nineteenth Asian Test Symposium (ATS), pp. 147-152, December 2010.
292. Y. Higami, K. K. Saluja, and H. Takahashi "Fault simulation and test generation for clock delay faults," Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), pp. 799-805, January 2011.
293. C. Yao, K. K. Saluja, and P. Ramanathan "Thermal-aware test scheduling using on-Chip temperature sensors," International Conference on VLSI Design , pp. 376-381, January 2011.
294. C. Yao, K. K. Saluja, and P. Ramanathan "Test Scheduling for Deep Submicron Technologies," International Conference on VLSI Design , January 2011. (Invited Paper)
295. Y.-T. Lin, K. K. Saluja, and S. Megerian "Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors," Journal of Ad Hoc Networks , pp. 713-726, vol. 9, no. 5, May 2011.
296. Chunhua Yao, Krishna Bharath, Kewal Saluja, Parameswaran Ramanathan, Nam Sung Kim "A Low Cost Approach to Calibrate On-Chip Thermal Sensors," International Symposium on Quality Electroing Design (ISQED), pp. 572-576, March 2011.
297. Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, Masahiro Fujita "SEU Tolerant SRAM Cell," International Symposium on Quality Electroing Design (ISQED), pp. 597-602, March 2011.
298. Warin Sootkaneung and Kewal K Saluja "Soft Error Reduction through Gate Input Dependent Weighted Sizing in Combinational Circuits," International Symposium on Quality Electroing Design (ISQED), pp. 603-610, March 2011.
299. C. Yao, Kewal K. Saluja, and P. Ramanathan "Power and thermal constrained test scheduling under deep submicron technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 317-322, February 2011.
300. Y. Higami, H. Takahashi, S.-Y. Kobayashi, and K. K. Saluja "Enhancment of clock delay fault testing," Eurpean Test Symposium (ETS), pp. 216, May 2011.
301. T. Iwagaki and K. K. Saluja "Indirect Detection of Clock Skew Induced Hold-Time Violations," IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 175-178, April 2011.
302. T. Iwagaki and K. K. Saluja, "Power-Constrained Test Generation for Hold-Time Faults Using Integer Linear Programming," Workshop on Impact of Low-Power Design on Test and Reliability (LPonTR), May 2011.
303. Chin-Ya Huang, P. Ramanatthan, and Kewal K. Saluja "Routing TCP Flows in Underwater Mesh Networks," IEEE Journal on Selected Areas in Communications (JSACS), pp. 2022-2032, vol. 29, no. 10, 2011.
304. C. Yao, Kewal K. Saluja, and P. Ramanathan "Calibrating On-Chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 711-721, vol. 27, no. 6, 2011.
305. Y. Higami, H. Takahashi, S. -Y. Kobayashi, and K. K. Saluja "On Detecting Transition Faults in the Presence of Clock Delay Faults," IEEE The Twentieth Asian Test Symposium (ATS), pp. 1-6, November 2011.
306. C. Yao, K. K. Saluja, and P. Ramanathan "Tepmerature Dependent Test Scheduling for Multi-core System-on-Chip," IEEE The Twentieth Asian Test Symposium (ATS), pp. 27-32, November 2011.
307. P. Subramanyan, V. Singh, K. K. Saluja and and E. Larsson " Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Mutiprocessors, " International Conference on Computer Design (ICCD), pp. 419--426, October 2011.
308. W. Sootkaneung and K. K. Saluja "Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate," International Conference on VLSI Design , pp. 74-79, January 2012.
309. Y. Higami, H. Takahashi, S. -Y. Kobayashi and K. K. Saluja "Diagnosis for Bridging Faults on Clock Lines," IEEE 2012 Pacific Rim International Symposium on Dependable Computing (PRDC12), pp. 135-144, December 2012.
310. S. Millican and K. K. Saluja "Linear Programming Formulation for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits," IEEE The Twenty First Asian Test Symposium (ATS), pp. 37-42, November 2012.
311. R. Ahmed, P. Ramanathan, K. K. Saluja, and C. Yao "Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems," International Conference on VLSI Design , pp. 25-30, January 2013.
312. L. Zhang, J. A. Ambrose, J. Peddersen, S. Parmeshwaran, R. G. Ragel, S. Radhakrishanan and K. K. Saluja "DRMA: Dynamically Reconfigurable MPoSC Architecture," Proceedings Great Lake Symposium on VLSI (GLSVLSI), pp. 239-244, May 2013.
313. Y. Higami, H. Takahashi, S. -Y. Kobayashi and K. K. Saluja "Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment," IEICE Transactions on Information and Systems , vol. E96-D, pp. 1323--1331, June 2013.
314. R. Ahmed, P. Ramanathan and K. K. Saluja "On Thermal Utilization of Periodic Task Sets in Uni-Processor Systems," IEEE Inernational Conference on Real-Time Computing Systems and Application (RTCSA), pp. xxx-yyy, August 2013.
315. S. Millican and K. K. Saluja "Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling," The Twenty Second Asian Test Symposium (ATS), pp. 165-170, November 2013.
316. K. Yamazaki, T. Tsutsumi, H. Takahashi, Y. Higami, H. Yostuyanagi, M. Hashizume, and K. K. Saluja "Diagnosing Resistive Open Faults using Small Delay Fault Simulation," The Twenty Second Asian Test Symposium (ATS), pp. 79-84, November 2013.
317. K. Le, P. Ramanathan, and K. K. Saluja "Privacy Assurances in Multiple Data-Aggregation Transactions," The 16th International Conference on Information Security and Cryptology, November 2013.
318. S. Millican, P. Ramanathan, and K. K. Saluja "CrytIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities," International Conference on VLSI Design , pp. 92-97, January 2014, Best Paper Award.
319. S. Millican and K. K. Saluja "Test Partitioning Technique for Scheduling Test for Thermally Constrained 3D Integrated Circuits," International Conference on VLSI Design , January 2014.
320. R. Ahmed, P. Ramanathan, and K. K. Saluja "Temperature Minimization Using Power Redistribution in Embedded Systems," International Conference on VLSI Design , pp. 264-269, January 2014.
321. Rehan Ahmed, Parameswaran Ramanathan, and Kewal K. Saluja "Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks," Euromicro Conference on Real-Time Systems {(ECRTS)}, pp. 243-252, July 2014.
322. S. Millcan and Kewal K. Saluja "Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling," Journal of Electronic Testing: Theory and Applications (JETTA), pp. 569-580, vol. 30, no. 5, 2014.
323. Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja "Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults," International Symposium on VLSI Design (ISVLSI) , pp. 320-325, July 2014. Best Paper Award
324. Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja "Diagnosis of Delay Faults in Multi-Clock SoCs," International TechInternational Technical Conference: Circuits, Systems, Computers and Communication (ITC-CSCC) , July 2014.
325. R. Ahmed, A. Bansal, B. Kakunoori, P. Ramanathan, and K. K. Saluja "Thermal Extension of the Total Bandwidth Server," International Symposium on VLSI Design , January 2015. Best Student Paper Award
326. S. Millican and K. K. Saluja "Optimal Test Scheduling of Stacked Circuits Under Various Hardware and Power Constraints," International Conference on VLSI Design , January 2015.

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Contact Information

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Copyright (c) 2002 Kewal K. Saluja, All Rights Reserved.

saluja@engr.wisc.edu